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GD32F310 Datasheet(PDF) 11 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32F310 Datasheet(HTML) 11 Page - GigaDevice Semiconductor (Beijing) Inc. |
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11 / 81 page  GD32F310xx Datasheet 10 2.2 Block diagram Figure 2-1. GD32F310xx block diagram NVIC TPIU SW Flash Memory Controller Flash Memory SRAM Controller SRAM AHB to APB Bridge 2 GP DMA 7chs USART0 SPI0/I2S0 ADC TIMER16 12-bit SAR ADC IBus ARM Cortex-M4 Processor Fmax: 72MHz POR/PDR PLL Fmax: 72MHz LDO 1.2V IRC8M 8MHz HXTAL 4-32MHz LVD EXTI TIMER0 AHB1: Fma x = 72MHz AHB to APB Bridge 1 CRC RST/CLK Controller DBus AHB2: Fma x = 72MHz GPIO Ports A, B, C, D, F IRC28M 28MHz TIMER14 TIMER15 IRC48M 48MHz Powered by LDO (1.2V) WWDGT SPI1 CTC I2C0 RTC FWDGT PMU I2C1 TIMER13 TIMER2 Powered by VDD/VDDA IRC40K 40KHz USART1 |
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