SRAM

AS5C4008

Austin Semiconductor, Inc.

AS5C4008

Rev. 5.5 12/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

NOTES

1.

All voltages referenced to V

2.

-2V for pulse width < 20ns

3.

I

4.

This parameter is guaranteed but not tested.

5.

Test conditions as specified with the output loading

as shown in Fig. 1 unless otherwise noted.

6.

are specified with CL = 5pF as in Fig. 2. Transition is

measured ±200mV from steady state voltage.

7.

At any given temperature and voltage condition,

8.

WE\ is HIGH for READ cycle.

9.

Device is continuously selected. Chip enables and

output enables are held in their active state.

10. Address valid prior to, or coincident with, latest

occurring chip enable.

12. Chip enable and write enable can initiate and

terminate a WRITE cycle.

13. Output enable (OE\) is inactive (HIGH).

14. Output enable (OE\) is active (LOW).

15. ASI does not warrant functionality nor reliability of any

product in which the junction temperature exceeds

150°C. Care should be taken to limit power to acceptable

levels.

Fig. 1 Output Load Equivalent

Fig. 2 Output Load Equivalent

167 ohms

167 ohms

1.73V

1.73V

C=5pF

C=30pF

Q

Q

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

AC TEST CONDITIONS

Input pulse levels ................................................... Vss to 3.0V

Input rise and fall times ....................................................... 3ns

Input timing reference levels ............................................ 1.5V

Output reference levels ..................................................... 1.5V

Output load ............................................... See Figures 1 and 2

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

NOTES

2V

Data Retention Current

(L Version Only)

4.5

mA

Chip Deselect to Data

Retention Time

0ns

4

Operation Recovery Time

10

ms

4, 11

CE\ > (Vcc -0.2V)

VIN > (Vcc -0.2V) or < 0.2V

CONDITIONS