CC2400-RTR1 datasheet(69/83 Pages) TI

69 / 83 page

CC2400

SWRS042A

Page 69 of 83

AGCTST0 (0x17) - AGC Test Register 0

Bit

Field Name

Reset

R/W

Description

15:13

AGC_SETTLE_BLANK_DN[2:

R/W

AGC blanking enable/limit for negative gain changes.

0: Disabled

1-7: Duration of blanking signal in 8 MHz clock cycles.

12:11

AGC_WIN_SIZE[1:0]

R/W

AGC window size.

10:7

AGC_SETTLE_PEAK[3:0]

R/W

AGC peak detectors settling period.

6:3

AGC_SETTLE_ADC[3:0]

R/W

AGC ADC settling period.

2:0

AGC_ATTEMPTS[2:0]

R/W

The maximum number of attempts to set the gain.

AGCTST1 (0x18) - AGC Test Register 1

Bit

Field Name

Reset

R/W

Description

Reserved, write as 0.

AGC_VAR_GAIN_SAT

R/W

Chooses the gain reduction upon saturation of the variable

gain stage:

0: -1/-3 gain steps

1: -3/-5 gain steps

13:11

AGC_SETTLE_BLANK_UP

[2:0]

R/W

AGC blanking enable/limit for positive gain changes.

0: Disabled

1-7: Duration of blanking signal in 8 MHz clock cycles.

PEAKDET_CUR_BOOST

R/W

Doubles the bias current in the peak-detectors in-between the

VGA stages when set.

9:6

AGC_MULT_SLOW[3:0]

R/W

AGC timing multiplier, slow mode.

5:2

AGC_SETTLE_FIXED[3:0]

R/W

AGC settling period, fixed gain step.

1:0

AGC_SETTLE_VAR[1:0]

R/W

AGC settling period, variable gain step.

AGCTST2 (0x19) - AGC Test Register 1

Bit

Field Name

Reset

R/W

Description

15:14

Reserved, write as 0.

13:12

AGC_BACKEND_BLANKING

[1:0]

R/W

AGC blanking makes sure that the modem locks its bit

synchronization and centre frequency estimator when the AGC

changes the gain.

0: Disabled

1-3: Fixed/variable enable

11:9

AGC_ADJUST_M3DB[2:0]

R/W

AGC parameter -3 dB.

8:6

AGC_ADJUST_M1DB[2:0]

R/W

AGC parameter -1 dB.

5:3

AGC_ADJUST_P3DB[2:0]

R/W

AGC parameter +3 dB.

2:0

AGC_ADJUST_P1DB[2:0]

R/W

AGC parameter +1 dB.

CC2400-RTR1 Datasheet(PDF) 69 Page - Texas Instruments

CC2400-RTR1 Datasheet(HTML) 69 Page - Texas Instruments

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