AM6412...ALV datasheet(196/244 Pages) TI

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CLOCKIN

DATAIN

PRPC1

PRPC3

PRPC2

PRPC4

PRPC5

PRU_TIMING_03

Figure 7-92. PRU_ICSSG PRU Parallel Capture Timing Requirements – Rising Edge Mode

CLOCKIN

DATAIN

PRPC1

PRPC2

PRPC3

PRPC5

PRU_TIMING_04

PRPC4

Figure 7-93. PRU_ICSSG PRU Parallel Capture Timing Requirements – Falling Edge Mode

7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing

Table 7-110. PRU_ICSSG PRU Timing Requirements – Shift In Mode

see Figure 7-94

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRSI1

tw(DATAINH)

Pulse duration, DATAIN high

2P(1) + 2

PRSI2

tw(DATAINL)

Pulse duration, DATAIN low

2P(1) + 2

(1)

P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register.

PRUn represents the respective PRU0 or PRU1 instance.

DATAIN

PRSI1

PRSI2

PRU_TIMING_05

Figure 7-94. PRU_ICSSG PRU Shift In Timing

Table 7-111. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode

see Figure 7-95

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRSO1

tc(CLOCKOUT)

Cycle time, CLOCKOUT

PRSO2L

tw(CLOCKOUTL)

Pulse duration, CLOCKOUT low

0.475P(1)Z(2) -

0.3

PRSO2H

tw(CLOCKOUTH)

Pulse duration, CLOCKOUT high

0.475P(1)Y(3) -

0.3

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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