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Table 7-106. OSPI0 Switching Characteristics – Tap DDR Mode (continued)

see Figure 7-90

NO.

PARAMETER

MODE

MIN

MAX

UNIT

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

(- 17.94 +

(0.975T(5)R(4)))

(- 1.56 +

(1.025T(5)R(4)))

(1)

P = CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = refclk cycle time in ns

(5)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 7-90. OSPI0 Switching Characteristics – Tap DDR, No Loopback

7.10.5.15 PCIe

The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the

specification for timing details.

For more details about features and additional description information on the device Peripheral Component

Interconnect Express, see the corresponding subsections within Signal Descriptions and Detailed Description

sections.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

7.10.5.16 PRU_ICSSG

The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication

Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU

cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast

real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks

from the other processor cores in the device.

For more details about features and additional description information on the device PRU_ICSSG, see the

corresponding subsections within Signal Descriptions and Detailed Description sections.

Note

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU

GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in

the device TRM.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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