TLV9152SIRUGR datasheet(13/77 Pages) TI

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6.7 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT

= VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SHUTDOWN

IQSD

Quiescent current per

amplifier

VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V– + 2 V

µA

ZSHDN

Output impedance during

shutdown

VS = 2.7 V to 16 V, amplifier disabled

10 || 2

GΩ || pF

VIH

Logic high threshold

voltage (amplifier

disabled)

For valid input high, the SHDN pin voltage should be greater than

the maximum threshold but less than or equal to V+

(V–) + 0.8 (V–) + 1.1

VIL

Logic low threshold

voltage (amplifier

enabled)

For valid input low, the SHDN pin voltage should be less than the

minimum threshold but greater than or equal to V–

(V–) + 0.2 (V–) + 0.8

tON

Amplifier enable time (1)

G = +1, VCM = V-, VO = 0.1 × VS/2

µs

tOFF

Amplifier disable time (1)

VCM = V-, VO = VS/2

µs

SHDN pin input bias

current (per pin)

VS = 2.7 V to 16 V, (V+) ≥ SHDN ≥ (V–) + 0.9 V

500

VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V

150

(1)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(2)

Specified by characterization only.

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TLV9151, TLV9152, TLV9154

SBOS986E – OCTOBER 2019 – REVISED JANUARY 2022

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