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TLV9152SIRUGR Datasheet(PDF) 11 Page - Texas Instruments

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Part # TLV9152SIRUGR
Description  TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
PDF  63 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLV9152SIRUGR Datasheet(HTML) 11 Page - Texas Instruments

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TLV9151, TLV9152, TLV9154
www.ti.com
SBOS986B – OCTOBER 2019 – REVISED MAY 2020
Product Folder Links: TLV9151 TLV9152 TLV9154
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2)
This package option is preview for TLV9152.
6.5 Thermal Information for Dual Channel
THERMAL METRIC (1)
TLV9152, TLV9152S
UNIT
D
(SOIC)
DDF (2)
(SOT-23-8)
DGK (2)
(VSSOP)
DGS (2)
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
RUG
(X2QFN)
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient
thermal resistance
138.7
TBD
TBD
TBD
77.6
185.1
142.3
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
78.7
TBD
TBD
TBD
93.7
74.0
53.5
°C/W
RθJB
Junction-to-board thermal
resistance
82.2
TBD
TBD
TBD
43.9
115.7
68.5
°C/W
ψJT
Junction-to-top
characterization parameter
27.8
TBD
TBD
TBD
4.4
12.3
1.0
°C/W
ψJB
Junction-to-board
characterization parameter
81.4
TBD
TBD
TBD
43.9
114.0
68.4
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
TBD
TBD
TBD
19.0
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2)
This package option is preview for TLV9154.
6.6 Thermal Information for Quad Channel
THERMAL METRIC (1)
TLV9154, TLV9154S
UNIT
D (2)
(SOIC)
PW (2)
(TSSOP)
RTE (2)
(WQFN)
RUC (2)
(WQFN)
14 PINS
14 PINS
16 PINS
16 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
TBD
TBD
TBD
TBD
TBD
°C/W
ψJB
Junction-to-board characterization
parameter
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
TBD
TBD
TBD
TBD
TBD
°C/W



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