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DS31256 Datasheet(PDF) 162 Page - Maxim Integrated Products |
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DS31256 Datasheet(HTML) 162 Page - Maxim Integrated Products |
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162 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 162 of 183 Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] LD[7:0] LD[15:8] LR/ W LDS Address Valid LBHE LRDY Tri-State Data Valid 12 3456789 10 Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set. |
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