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DS31256 Datasheet(PDF) 159 Page - Maxim Integrated Products |
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DS31256 Datasheet(HTML) 159 Page - Maxim Integrated Products |
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159 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 159 of 183 Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted ( LBGACK deasserted), the timing shown at the top of the page occurs, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been granted ( LBGACK asserted), the timing shown at the bottom of the page applies. LCLK LBR LBG LBGACK 32 to 1,048,576 LCLKs LA[19:0] LD[7:0] LD[15:8] LR /W LDS Address Valid Data Valid LBHE Tri-State Tri-State Tri-State Tri-State LCLK 123456 Note: LA, LD, LBHE, LDS, and LR/W are tri-stated. |
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