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1024 Datasheet (PDF) - Lattice Semiconductor

1024 Datasheet PDF - Lattice Semiconductor
Part No. 1024
Download  1024 Click to view

File Size   147.19 Kbytes
Page   12 Pages
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor
Description In-System Programmable High Density PLD

1024 Datasheet (PDF)

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1024 Datasheet PDF - Lattice Semiconductor

Part No. 1024
Download  1024 Click to view

File Size   147.19 Kbytes
Page   12 Pages
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor
Description In-System Programmable High Density PLD

1024 Datasheet (HTML) - Lattice Semiconductor

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1024 Product details

Description
The ispLSI 1024/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 144 Registers, 48 Universal I/O pins, six Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP).
   
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
    — High-Speed Global Interconnect
    — 4000 PLD Gates
    — 48 I/O Pins, Six Dedicated Inputs
    — 144 Registers
    — Wide Input Gating for Fast Counters, State
        Machines, Address Decoders, etc.
    — Small Logic Block Size for Fast Random Logic
    — Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 60 MHz Maximum Operating Frequency
    — tpd = 20 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and Reprogrammable
    — Non-Volatile E2CMOS Technology
    — 100% Tested
• IN-SYSTEM PROGRAMMABLE
    — In-System Programmable™ (ISP™) 5-Volt Only
    — Increased Manufacturing Yields, Reduced Time-toMarket,
        and Improved Product Quality
    — Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
    SPEED OF PLDs WITH THE DENSITY AND
    FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
    — Complete Programmable Device Can Combine Glue
        Logic and Structured Designs
    — Four Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global
        Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND
    COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
    SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
    — Superior Quality of Results
    — Tightly Integrated with Leading CAE Vendor Tools
    — Productivity Enhancing Timing Analyzer, Explore
        Tools, Timing Simulator and ispANALYZER™
    — PC and UNIX Platforms
   



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