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ISPLSI3256E Datasheet (PDF) - Lattice Semiconductor

ISPLSI3256E Datasheet PDF - Lattice Semiconductor
Part No. ISPLSI3256E
Download  ISPLSI3256E Click to view

File Size   251.82 Kbytes
Page   15 Pages
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor
Description In-System Programmable High Density PLD

ISPLSI3256E Datasheet (PDF)

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ISPLSI3256E Datasheet PDF - Lattice Semiconductor

Part No. ISPLSI3256E
Download  ISPLSI3256E Click to view

File Size   251.82 Kbytes
Page   15 Pages
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor
Description In-System Programmable High Density PLD

ISPLSI3256E Datasheet (HTML) - Lattice Semiconductor

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ISPLSI3256E Product details

Description
The ispLSI 3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements.

Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
    — 256 I/O Pins
    — 12000 PLD Gates
    — 512 Registers
    — High Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 100 MHz Maximum Operating Frequency
    — tpd = 10 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and Reprogrammable
    — Non-Volatile
    — 100% Tested at Time of Manufacture
    — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
    — 5V In-System Programmable (ISP™) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol
    — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
    — Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
    — Complete Programmable Device Can Combine Glue Logic and Structured Designs
    — Five Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Programmable Output Slew Rate Control to Minimize Switching Noise
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
    — Superior Quality of Results
    — Tightly Integrated with Leading CAE Vendor Tools
    — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
    — PC and UNIX Platforms



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