TFP201, TFP201A

TI PanelBus DIGITAL RECEIVER

SLDS116A - MARCH 2000 – REVISED JUNE 2000

3

POST OFFICE BOX 655303

functional block diagram

_

+

Latch

Channel 2

_

+

Latch

Channel 1

_

+

Latch

Channel 0

_

+

PLL

Data Recovery

and

Synchronization

TMDS

Decoder

CH2(0-9)

CH1(0-9)

CH0(0-9)

Panel

Interface

RED(0-7)

CTL3

CTL2

GRN(0-7)

CTL1

BLU(0-7)

VSYNC

HSYNC

QE(0-23)

QO(0-23)

ODCK

DE

SCDT

CTL3

CTL2

CTL1

VSYNC

HSYNC

1.8 V

Regulator

3.3 V

Internal 50-

Ω

Termination

3.3 V

3.3 V

Rx2+

Rx2-

Rx1+

Rx1-

Rx0+

Rx0-

RxC+

RxC-

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

79,83,87,

89,92

GND

Analog Ground – Ground reference and current return for analog circuitry.

AVDD

82,84,88,

95

VDD

Analog VDD – Power supply for analog circuitry. Nominally 3.3 V

CTL[3:1]

42,41,40

DO

General-purpose control signals – Used for user defined control. CTL1 is not powered-down via PDO.

DE

46

DO

Output data enable – Used to indicate time of active video display versus non-active display or blank time.

During blank, only HSYNC, VSYNC, and CTL1-3 are transmitted. During times of active display, or non-blank,

only pixel data, QE[23:0] and QO[23:0], is transmitted.

High : Active display time

Low: Blank time

DFO

1

DI

Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For

TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high, otherwise

ODCK is held low when DE is low.

High : DSTN support/ODCK held low when DE = low

Low: TFT support/ODCK runs continuously.

DGND

5,39,68

GND

Digital ground – Ground reference and current return for digital core

DVDD

6,38,67

VDD

Digital VDD – Power supply for digital core. Nominally 3.3 V

EXT_RES

96

AI

Internal impedance matching – The TFP201/201A is internally optimized for impedance matching at 50

Ω. An

external resistor tied to this pin will have no effect on device performance.

HSYNC

48

DO

Horizontal sync output

RSVD

99

DI

Reserved. Must be tied high for normal operation.

OVDD

18,29,43,

57,78

VDD

Output driver VDD – Power supply for output drivers. Nominally 3.3 V

ODCK

44

DO

Output data clock - Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with

DE, HSYNC, VSYNC and CTL[3:1] are synchronized to this clock.