TNETV2664FIBZWT datasheet(99/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

•

PCI Data Block

–

AD30

–

AD28

–

AD26

3.7.3.2

Peripherals Spanning Multiple Pin Mux Blocks

Some peripherals span multiple Pin Mux Blocks. To use these peripherals, they must be selected in all of

the relevant Pin Mux Blocks. The following is the list of peripherals that span multiple Pin Mux Blocks:

•

PCI: PCI pins span across the Host Block, EMIFA Block Sub-Block 0 and Sub-Block 3, PCI Data

Block, and GPIO Block. To select PCI pins, program PINMUX registers as follows:

–

Host Block: PCIEN = 1, HOSTBK = 000

–

EMIFA Block: Select either Major Configuration Option G, H, J, or K. For more details on the

PINMUX settings associated with Major Configuration Options G, H, J, or K, see Section 3.7.3.13,

EMIFA Block Muxing.

–

PCI Data Block: PCIEN = 1

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GPIO Block: PCIEN = 1

•

McBSP0: Six McBSP0 pins are located in the Serial Port Sub-Block 0, but the CLKS0 pin is muxed in

the Timer0 Block. To select McBSP0 pins, program PINMUX registers as follows:

–

Serial Port Sub-Block 0: SPBK0 = 01

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Timer0 Block: If CLKS0 pin is desired, program TIM0BK = 10 or 11.

•

McBSP1: Six McBSP1 pins are located in the Serial Port Sub-Block 1, but the CLKS1 pin is muxed in

the Timer0 Block. To select McBSP1 pins, program PINMUX registers as follows:

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Serial Port Sub-Block 1: SPBK1 = 01 (if both McBSP1 transmit and receive pins are needed) or

11 (if only McBSP1 transmit pins are needed)

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Timer0 Block: If CLKS1 pin is desired, program TIM0BK = 10.

Device Configurations

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