PL138-48OC-R datasheet(11/20 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005543B-page 11

PL138-48

FIGURE 5-8:

CLK-IN Input Driven by a

Single-Ended LVPECL.

FIGURE 5-9:

CLK-IN Input Driven by an

HCSL Driver.

HCSL presents its signals very close to the ground rail,

below the VCMR range, so the HCSL signals cannot be

connected to the PL138 input directly. AC-coupling is

required for HCSL signals on the PL138 input.

FIGURE 5-10:

Input Logic Block Diagram.

5.2

Termination for LVPECL Outputs

The required termination for LVPECL is 50Ω to a

VCC-2V DC voltage level. Below are two schematics to

implement this termination.

FIGURE 5-11:

LVPECL Termination

Schematic #1.

•VCC = 3.3V

- Ideal values: R1 = 127Ω, R2 = 82.5Ω

- Commercial values (E24): R1 = 130Ω,

R2 = 82Ω

•VCC = 2.5V

- Ideal values: R1 = 250Ω, R2 = 62.5Ω

- Commercial values (E24): R1 = 240Ω,

R2 = 62Ω

TABLE 5-1:

INPUT PIN

CHARACTERISTICS

Input

Parameter Min. Typ. Max. Units

CLK-IN0,

CLK-IN1

Pull-Down

Resistor

—75

—

kΩ

CLK-IN0B,

CLK_IN1B

Pull-Up &

Pull-Down

Resistors

—100

—

CLK-EN

Pull-Up

Resistor

—50

—

CLKSEL

Pull-Down

Resistor

—50

—

TABLE 5-2:

INPUT CLOCK CONTROL

SELECTION

CLK_SEL

Selected Source

0CLK-IN0

1CLK-IN1

TABLE 5-3:

INPUT CLOCK FUNCTION

Inputs

Outputs

CLK-EN CLKSEL Source

Q0:Q3

Q0B:Q3B

CLK-IN0 Disabled

Low

Disabled

High

CLK-IN1 Disabled

Low

Disabled

High

CLK-IN0 Enabled

Enabled

CLK-IN1 Enabled

Enabled

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