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TPS62320 Datasheet(PDF) 21 Page - Texas Instruments |
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TPS62320 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 31 page ![]() www.ti.com THERMAL INFORMATION P D(MAX) + T J(MAX) * T A R q JA + 125°C * 85°C 250 °C W + 160 mW (6) CHIP SCALE PACKAGE DIMENSIONS TPS62300, TPS62301, TPS62302 TPS62303, TPS62305, TPS62311 TPS62313, TPS62320, TPS62321 SLVS528B – JULY 2004 – REVISED JUNE 2005 Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the power-dissipation limits of a given component Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow in the system The maximum recommended junction temperature (TJ) of the TPS6230x, TPS6231x, and TPS6232x devices is 125 °C. The thermal resistance of the 8-pin CSP package (YZD and YED) is Rθ JA = 250°C/W. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 160 mW. More power can be dissipated if the maximum ambient temperature of the application is lower or if the PowerPAD™ package (DRC) is used. The TPS6230x, TPS6231x, and TPS6232x are also available in an 8-bump chip scale package (YZD, NanoFree™ and YED, NanoStar™). The package dimensions are given as: • D = 1.970 ±0.05 mm • E = 0.970 ±0.05 mm 21 |
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