TPS62320 datasheet(19/31 Pages) TI

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INPUT CAPACITOR SELECTION

CHECKING LOOP STABILITY

PROGRAMMING THE OUTPUT VOLTAGE WITH A DAC

AVIN

VIN

TPS62300

ADJ

PGND

AGND

VOUT

MODE/SYNC

VO = 1.5 x V(DAC)

V(DAC)

10 kW

TPS62300, TPS62301, TPS62302

TPS62303, TPS62305, TPS62311

TPS62313, TPS62320, TPS62321

SLVS528B – JULY 2004 – REVISED JUNE 2005

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required to prevent large voltage transients that can cause misbehavior of the device or interferences with other

circuits in the system. For most applications, a 2.2-

µF or 4.7-µF capacitor is sufficient.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the

power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce

ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even

damage the part.

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

•

Switching node, SW

•

Inductor current, IL

•

Output ripple voltage, V

O(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the

switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the

regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between

the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply

all of the current required by the load. VO immediately shifts by an amount equal to ∆I(LOAD) x ESR, where ESR

is the effective series resistance of CO. ∆I(LOAD) begins to charge or discharge CO generating a feedback error

signal used by the regulator to return VO to its steady-state value.

During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the

converter’s stability. Without any ringing, the loop has usually more than 45

° of phase margin.

Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET

rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,

load current range, and temperature range.

On TPS62300 and TPS62320 devices, the output voltage can be dynamically programmed to any voltage

between 0.6 V and VI (or 5.4 V whichever is lower) with an external DAC driving the ADJ and FB pins (see

Figure 33). The output voltage is then equal to A(PT) x V(DAC) with a Power Train amplification A(PT) typical = 1.5.

When the output voltage is driven low, the converter reduces its output quickly in forced PWM mode, boosting

the output energy back to the input. If the input is not connected to a low-impedance source capable of absorbing

the energy, the input voltage can rise above the absolute maximum voltage of the part and get damaged. The

faster VO is commanded low, the higher is the voltage spike at the input.

For best results, ramp the ADJ/FB signal as slow as the application allows. To avoid over-slew of the regulation

loop of the converter, avoid abrupt changes in output voltage of > 300 mV/

µs (depending on V

I , output voltage

step size and L/C combination). If ramp control is unavailable, an RC filter can be inserted between the DAC

output and ADJ/FB pins to slow down the control signal.

Figure 33. Filtering the DAC Voltage

TPS62320 Datasheet(PDF) 19 Page - Texas Instruments

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