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ATFS05/10/40

3017C–FPSLI–07/02

Pin Description

8LAP

Pin

Name

I/O

Description

1

DATA

I/O

Tri-state DATA output for configuration. Open-collector bi-directional pin for programming.

2CLK

I

Clock input. Used to increment the internal address and bit counter for reading and programming.

3

RESET/

OE

I

Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on

RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the

data output driver.

4CE

I

Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the

address counter and enables the data output driver. A High level on CE disables both the

address and bit counters and forces the device into a low-power standby mode. Note that this

pin will

not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low).

5

GND

Ground pin. A 0.2 µF decoupling capacitor between

6

A2

I

Device selection input, A2. This is used to enable (or select) the device during programming

(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.

7

SER_EN

I

Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low

enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be

+3.3V power supply pin