EM3592-RTR datasheet(49/59 Pages) SILABS

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EM359x

Rev 1.0

PC2

I/O

Digital I/O

Enable with GPIO_DBGCFG[5] and GPIO_PCCFGH[1] clear

JTDO

JTAG data out to debugger

Selected when in JTAG mode (default mode, see JTMS description,

Pin 42)

SWO

Serial Wire Output asynchronous trace output to debugger

Select asynchronous trace interface in ARM core

Enable trace interface in ARM core

Select alternate output function with GPIO_PCCFGL[11:8]

Enable Serial Wire mode (see JTMS description, Pin 42)

Internal pull-up is enabled

TRACEDATA0

Synchronous CPU trace data bit 3

Select 4-wire synchronous trace interface in ARM core

Enable trace interface in ARM core

Select alternate output function with GPIO_PACFGL[11:8]

PC3

I/O

Digital I/O

Either Enable with GPIO_DBGCFG[5],



or enable Serial Wire mode (see JTMS description, Pin 42)

JTDI

JTAG data in from debugger

Selected when in JTAG mode (default mode, see JTMS description,

Pin 42)

Internal pull-up is enabled

TRACECLK

Synchronous CPU trace clock

Enable trace interface in ARM core

Select alternate output function with GPIO_PCCFGL[15:12]

PC4

I/O

Digital I/O

Enable with GPIO_DBGCFG[5]

JTMS

JTAG mode select from debugger

Selected when in JTAG mode (default mode)

JTAG mode is enabled after power-up or by forcing nRESET low

Select Serial Wire mode using the ARM-defined protocol through a debug-

ger

Internal pull-up is enabled

SWDIO

I/O

Serial Wire bidirectional data to/from debugger

Enable Serial Wire mode (see JTMS description)

Select Serial Wire mode using the ARM-defined protocol through a debug-

ger

Internal pull-up is enabled

Table 6.1. EM359x Pin Descriptions (Continued)

Pin #

Signal

Direction

Description

Note:

IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and

GPIO_IRQDSEL registers.

EM3592-RTR Datasheet(PDF) 49 Page - Silicon Laboratories

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