Improved, Quad, SPST Analog Switches

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7

tOFF

0.8 x VOUT

VOUT

0.8 x VOUT

50%

0V

0V

+3V

SWITCH

OUTPUT

LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

tON

SWITCH

INPUT

LOGIC

INPUT

+3V

IN

D

+15V

V+

V-

-15V

RL

35pF

VOUT

S

CL (INCLUDES FIXTURE AND STRAY CAPACITANCE)

GND

REPEAT TEST FOR CHANNELS 2, 3, AND 4.

VOUT = VD

LOGIC

INPUT

DG441

DG442

(

)

∆VOUT

OFF

ON

OFF

VOUT

IN

IN

OFF

OFF

ON

Q =

∆VOUT × CL

-15V

V-

V+

IN

GND

S

+15V

RGEN

VGEN

VIN = +3V

CL

1nF

VOUT

D

DG441

DG442

DG441

DG442

Figure 2. Switching Time

Figure 3. Charge Injection

NETWORK

ANALYZER

SIGNAL

GENERATOR

RGEN = 50Ω

S

D

GND

RL

10dBm

10nF

V+

+15V

IN

0.8V or 2.4V

V-

-15V

10nF

DG441

DG442

NETWORK

ANALYZER

SIGNAL

GENERATOR

RGEN = 50Ω

0.8V or 2.4V

S

IN1

D

GND

RL

10dBm

10nF

V+

+15V

D

IN2

S

0.8V or 2.4V

50

Ω

V-

-15V

10nF

DG441

DG442

Figure 4. Off-Isolation Rejection Ratio

Figure 5. Crosstalk (repeat for channels 3 and 4)

______________________________________________Timing Diagrams/Test Circuits