STAC9708 datasheet(22/56 Pages) ETC

22 / 56 page

SigmaTel, Inc.

Preliminary

STAC9708/11

10/02/98

Figure 10. STAC9708/11 Powerdown Timing

SYNC

BIT_CLK

SDATA_OUT

per frame

SDATA_IN

slot2

TAG

Write to

Data

slot2

TAG

per frame

0x20

PR4

Note: BIT_CLK not to scale

BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following

the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at

the point where it is ready to program the AC-Link into its low power mode, slots (1 and 2) are assumed to

be the only valid stream in the audio output frame (all sources of audio input have been neutralized).

The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9708/11

to this low power mode.

3.2.1 Waking up the AC-Link

Once the STAC9708/11 has halted BIT_CLK, there are only two ways to “wake up” the AC-Link.

Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a “Cold

AC'97 Reset”, and a “Warm AC'97 Reset”. The current power down state would ultimately dictate

which form of reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset register) is

performed, wherein the AC'97 registers are initialized to their default values, registers are required to

keep state during all power down modes. Once powered down, re-activation of the AC-Link via re-

assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame

in which the power down was triggered. When AC-Link powers up it indicates readiness via the Codec

Ready bit (input slot 0, bit 15).

Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time. By driving

RESET# low, BIT_CLK, and SDATA_IN will be activated, or re-activated as the case may be, and all

STAC9708/11 control registers will be initialized to their default power on reset values.

Note: RESET# is an asynchronous input.

# denotes active low

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