STM32F101VC datasheet(90/112 Pages) STMICROELECTRONICS

90 / 112 page

Electrical characteristics

STM32F101xC, STM32F101xD, STM32F101xE

90/112

Doc ID 14610 Rev 8

Table 54.

SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

DuCy(SCK)

SPI slave input clock duty

cycle

Slave mode

tsu(NSS)

(1)

NSS setup time

Slave mode

4tPCLK

th(NSS)

(1)

NSS hold time

Slave mode

2tPCLK

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master mode, fPCLK = 36 MHz,

presc = 4

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master mode

Slave mode

th(MI)

(1)

Data input hold time

Master mode

th(SI)

(1)

Slave mode

ta(SO)

(1)(2)

Data output access time

Slave mode, fPCLK = 20 MHz

3tPCLK

tdis(SO)

(1)(3)

Data output disable time

Slave mode

tv(SO)

(1)(1)

Data output valid time

Slave mode (after enable edge)

tv(MO)

(1)(1)

Data output valid time

Master mode (after enable edge)

th(SO)

(1)

Data output hold time

Slave mode (after enable edge)

th(MO)

(1)

Master mode (after enable edge)

Based on characterization, not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

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