Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

OC1AI Datasheet(PDF) 21 Page - ATMEL Corporation

Part # OC1AI
Description  High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture
PDF  294 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

OC1AI Datasheet(HTML) 21 Page - ATMEL Corporation

Back Button OC1AI Datasheet HTML 17Page - ATMEL Corporation OC1AI Datasheet HTML 18Page - ATMEL Corporation OC1AI Datasheet HTML 19Page - ATMEL Corporation OC1AI Datasheet HTML 20Page - ATMEL Corporation OC1AI Datasheet HTML 21Page - ATMEL Corporation OC1AI Datasheet HTML 22Page - ATMEL Corporation OC1AI Datasheet HTML 23Page - ATMEL Corporation OC1AI Datasheet HTML 24Page - ATMEL Corporation OC1AI Datasheet HTML 25Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 294 page
background image
21
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 3-2.
Data Memory Map
3.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 3-3.
Figure 3-3.
On-chip Data SRAM Access Cycles
3.3
EEPROM Data Memory
The Atmel® AVR® contains EEPROM memory (see “E2 size” in Table 3-1 on page 19). It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The
access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control
Register.
Section 22. “Memory Programming” on page 236 contains a detailed description on EEPROM
programming in SPI or Parallel Programming mode.
32 Registers
64 I/O Registers
Internal SRAM
(ISRAM size)
0x0000 - 0x001F
0x0020 - 0x005F
ISRAM end
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
ISRAM start
clk
WR
RD
Data
Data
Address
Address valid
T1
T2
T3
Compute Address
CPU
Memory Access Instruction
Next Instruction



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link to Datasheet   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com