MPC8349CVVALDB datasheet(25/87 Pages) FREESCALE

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 10 shows the GMII receive AC timing diagram.

Figure 10. GMII Receive AC Timing Diagram

8.2.2

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.2.1

MII Transmit AC Timing Specifications

Table 27 provides the MII transmit AC timing specifications.

RX_CLK clock rise (20%–80%)

tGRXR

——

1.0

RX_CLK clock fall time (80%–20%)

tGRXF

——

1.0

Note:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing

(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going

to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. In general, the clock

reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGRX

represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

Table 27. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—400

—

TX_CLK clock period 100 Mbps

tMTX

—40—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

Table 26. GMII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKH

RX_DV

RX_ER

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