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MPC8314VRADDA Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc |
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MPC8314VRADDA Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 101 page ![]() MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 27 Ethernet: Three-Speed Ethernet, MII Management This figure provides the AC test load. Figure 13. AC Test Load This figure shows the RMII receive AC timing diagram. Figure 14. RMII Receive AC Timing Diagram 9.2.3 RGMII and RTBI AC Timing Specifications This table presents the RGMII and RTBI AC timing specifications. RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK tRMRDVKH 4.0 — — ns RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK tRMRDXKH 2.0 — — ns REF_CLK clock rise VIL(min) to VIH(max) tRMXR 1.0 — 4.0 ns REF_CLK clock fall time VIH(max) to VIL(min) tRMXF 1.0 — 4.0 ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Table 29. RGMII and RTBI AC Timing Specifications At recommended operating conditions (see Table 2) Parameter/Condition Symbol 1 Min Typ Max Unit Data to clock output skew (at transmitter) tSKRGT –0.6 — 0.6 ns Data to clock input skew (at receiver) 2 tSKRGT 1.0 — 2.6 ns Table 28. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with LVDD of 3.3 V ± 300 mv Parameter/Condition Symbol 1 Min Typ Max Unit Output Z0 = 50 NVDD/2 RL = 50 REF_CLK RXD[1:0] tRMRDXKH tRMX tRMXH tRMXR tRMXF CRS_DV RX_ER tRMRDVKH Valid Data |
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