ADP1655ACBZ-R7 datasheet(21/24 Pages) AD

21 / 24 page

ADP1655

Rev. 0 | Page 21 of 24

The worst-case capacitance accounting for capacitor variation

over temperature, component tolerance, and voltage is calcu-

lated using the following equation:

CEFF = COUT × (1 − TEMPCO) × (1 − TOL)

where:

CEFF is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, TEMPCO over −40°C to +85°C is assumed to

be 15% for an X5R dielectric, TOL is assumed to be 10%, and

COUT is 9.528 μF at 1.8 V, as shown in Figure 35.

Substituting these values in the equation yields

CEFF = 9.528 μF × (1 − 0.15) × (1 − 0.1) = 7.288 μF

DC BIAS VOLTAGE (V)

101214

Figure 35. DC Bias Characteristic of a 16 V, 10 μF Ceramic Capacitor

To guarantee the performance of the ADP1655, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

()

OUT

RIPPLE

OUT

RIPPLE

Capacitors with lower equivalent series resistance (ESR) are

preferred to guarantee low output voltage ripple, as shown in

the following equation:

RIPPLE

COUT

ESR

≤

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is 4 μF.

ADP1655ACBZ-R7 Datasheet(PDF) 21 Page - Analog Devices