SRAM

SRAM

SRAM

SRAM

SRAM

AS5LC512K8

AS5LC512K8

Rev. 2.1 08/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

Austin Semiconductor, Inc.

Input pulse levels ...................................................... Vss to 3.0V

Input rise and fall times ......................................................... 3ns

Input timing reference levels ............................................... 1.5V

Output reference levels ........................................................ 1.5V

Output load ................................................. See Figures 1 and 2

NOTES

1.

All voltages referenced to V

2.

I

ADDR, ADDR\, ADDR, etc.

3.

I

4.

This parameter is guaranteed but not tested.

5.

Test conditions as specified with the output loading

as shown in Fig. 1 unless otherwise noted.

6.

are specified with CL = 5pF as in Fig. 2. Transition is

measured ±200mV from steady state voltage.

7.

At any given temperature and voltage condition,

8.

WE\ is HIGH for READ cycle.

9.

Device is continuously selected. Chip enables and

output enables are held in their active state.

10. Address valid prior to, or coincident with, latest

occurring chip enable.

12. Chip enable and write enable can initiate and

terminate a WRITE cycle.

13. Output enable (OE\) is inactive (HIGH).

14. Output enable (OE\) is active (LOW).

15. ASI does not warrant functionality nor reliability of

any product in which the junction temperature

exceeds 150°C. Care should be taken to limit power to

acceptable levels.

Fig. 1 Output Load Equivalent

Fig. 2 Output Load Equivalent

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

AC TEST CONDITIONS

DESCRIPTION

SYM

MIN

MAX

UNITS

NOTES

Vcc for Retention Data

2V

Data Retention Current

Vcc = 2.0V

6.5

mA

Chip Deselect to Data

0ns

4

Operation Recovery Time

20

ms

4, 11

CONDITIONS

3.3V

Q

353

Ω

5 pF

319

Ω

Q

30 pF

R

L

= 50

Ω

V

L

= 1.5V

Z