M30620FCAFP datasheet(553/615 Pages) RENESAS

553 / 615 page

External Buses

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-236

4.4.2 Connecting Low-Speed Memory

To connect memory with long access time [ta(A)], either decrease the frequency of BCLK or set a soft-

________

ware wait. Using the RDY feature allows you to connect memory having the timing that precludes con-

nection though you set software wait.

(1) Using software wait

Set software wait by using either of bit 7 (PM17) of processor mode register 1 or bits 4 through 7

(CS0W through CS3W) of the chip select control register. With software wait set, if an address space

is accessed in which a separate bus is selected, the bus cycle results in two cycles of BCLK; if an

address space is accessed in which a multiplex bus is selected, the bus cycle results in three cycles of

BCLK.

If bit 7 (PM17) of processor mode register 1 is set to “Wait selected”, the microcomputer accesses

every area with this option in effect. If bit 7 (PM17) of processor mode register 1 is set to “Wait

cleared”, the Wait option can be either selected or cleared, chip select by chip select, by setting bits

4 through 7 (CS0W through CS3W) of the chip select control register. Figures 4.4.3 through 4.4.5

show relation of processor mode and the wait bit (PM17, CSiW).

Figure 4.4.3. Relation of processor mode and the wait bit (PM17, CSiW) (1)

BCLK X 2

BCLK X 1

SFR area

Internal RAM area

Internal ROM area

Single-chip mode

(When, PM17 = “0”)

0000016

0040016

FFFFF16

E800016

02C0016

BCLK X 2

SFR area

Internal RAM area

Single-chip mode

(When, PM17 = “1”)

0000016

0040016

BCLK X 2

Internal ROM area

FFFFF16

02C0016

E800016

In case of M30620MAA

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