M30620FCAFP datasheet(549/615 Pages) RENESAS

549 / 615 page

External Buses

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-232

4.4 Connectable Memories

4.4.1 Operation Frequency and Access Time

Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to

that of the BCLK , and is contingent on the oscillator's frequency and on the settings in the system clock

select bits (bit 6 of address 000616, and bits 6 and 7 of address 000716).

The following are the conditional equations for the connections. Meet these conditions minimally. Fig-

ures 4.4.1 and 4.4.2 show the relation between the frequency of BCLK and memory.

(1) Read cycle time (tCR)/write cycle time (tCW)

Read cycle time (tCR) and write cycle time (tCW) must satisfy the following conditional expressions:

• With the Wait option cleared

tCR < 109/f(BCLK) and tCW < 109/f(BCLK)

• With the Wait option selected

tCR < 2 X 109/f(BCLK) and tCW < 2 X 109/f(BCLK)

(2) Address access time [ta(A)]

Address access time [ta(A)] must satisfy the following conditional expressions:

(a) Vcc = 5V

• With the Wait option cleared

ta(A) < 109/f(BCLK) – 65(ns)*

• With the Wait option selected

ta(A) < 2 X 109/f(BCLK) – 65(ns)*

* 65(ns)

= td(BCLK – AD) + tsu(DB – RD) – th(BCLK – RD)

= (address output delay time) + (data input setup time) – (RD signal output hold time)

(b) Vcc = 3V

• With the Wait option cleared

ta(A) < 109/f(BCLK) – 140(ns)*

• With the Wait option selected

ta(A) < 2 X109/f(BCLK) – 140(ns)*

* 140(ns) = td(BCLK-AD) + tsu(DB – RD) – th(BCLK – RD)

= (address output delay time) + (data input setup time) – (RD signal output hold time)

(3) Chip select access time [ta(S)]

Chip select access time [ta(S)] must satisfy the following conditional expressions:

(a) Vcc = 5V

• With the Wait option cleared

ta(S) < 109/f(BCLK) – 65(ns)*

• With the Wait option selected

ta(S) < 2 X109/f(BCLK) – 65(ns)*

* 65(ns)

= td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD)

= (chip select output delay time) + (data input setup time) – (RD signal output hold time)

M30620FCAFP Datasheet(PDF) 549 Page - Renesas Technology Corp

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