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M30620FCAFP Datasheet(PDF) 424 Page - Renesas Technology Corp |
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M30620FCAFP Datasheet(HTML) 424 Page - Renesas Technology Corp |
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424 / 615 page ![]() SI/O3, 4 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2-107 Figure 2.6.2. Serial I/O3, 4-related registers SI/Oi bit rate generator (Note 1, 2) b7 b0 Symbol Address When reset S3BRG 036316 Indeterminate S4BRG 036716 Indeterminate Indeterminate Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set W R SI/Oi transmit/receive register (Note) b7 b0 Symbol Address When reset S3TRR 036016 Indeterminate S4TRR 036416 Indeterminate Indeterminate Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. W R S I/Oi control register (i = 3, 4) (Note 1) Symbol Address When reset SiC 036216, 036616 4016 b7 b6 b5 b4 b3 b2 b1 b0 W R Description SMi5 SMi1 SMi0 SMi3 SMi6 SMi7 Internal synchronous clock select bit Transfer direction select bit S I/Oi port select bit (Note 2) SOUTi initial value set bit 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Must not be set. b1 b0 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output 0 : Input-output port 1 : SOUTi output, CLK function Bit name Bit symbol Synchronous clock select bit (Note 2) 0 : LSB first 1 : MSB first SMi2 SOUTi output disable bit 0 : SOUTi output 1 : SOUTi output disable(high impedance) Note 1: Set “1” in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to “0”, be sure to set the sync clock select bit to “1”. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Note: Write a value to this register while transmit/receive halts. |
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