M30620FCAFP datasheet(421/615 Pages) RENESAS

421 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-104

UART

2.5.7 Error-permitted range range of transfer baud

<1ST-8DATA-1SP>

At the falling edge of ST, the transfer clock is

generated, and reception starts.

When the transfer rate of

the receive data is faster

than the rate of the transfer

clock on the receiver side

RxDi

(Receive data)

Transfer clock

(Receiver side)

1 clock

8 clocks

9.5 clocks

ST : Start bit

SP : Stop bit

∗ 1 period of BRGi's count source (Maximum)

••• According to the condition of the input timing,

a maximum of this period (

∗) can be omitted.

∗

SP must be detected at

this last rising edge of

the transfer clock.

When the transfer rate of

the receive data is slower

than the rate of the transfer

clock on the receiver side

1 clock

During reception, the receive data input to the RXDi pin is taken at the rising edge of the transfer clock.

Accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of one-

set receive data rises last. Figure 2.5.21 shows the relationship between the transfer clock and receive

data.

Figure 2.5.21 Relationship between transfer clock and receive data

M30620FCAFP Datasheet(PDF) 421 Page - Renesas Technology Corp