M30620FCAFP datasheet(385/615 Pages) RENESAS

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Clock-Synchronous Serial I/O

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-68

In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3.

Operations of the circled items are described below. Figure 2.4.13 shows the operation timing, and Fig-

ures 2.4.14 and 2.4.15 show the set-up procedures.

2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)

Item

Set-up

Transfer clock

source

CLK polarity

Internal clock (f1 / f8 / f32)

External clock (CLKi pin)

RTS function

RTS function enabled

RTS function disabled

Input reception data at

the rising edge of the

transfer clock

Input reception data at

the falling edge of the

transfer clock

Continuous receive

mode

Disabled

Enabled

Output transfer clock

to multiple pins

(Note 1)

Not selected

Selected

Transfer clock

LSB first

MSB first

Data logic select

function

(Note 2)

No reverse

Reverse

TXD, RXD I/O

polarity reverse bit

(Note 2)

No reverse

Reverse

Table 2.4.3. Choosed functions

Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is

_______ _______

selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”.

Note 2: UART2 only.

Operation (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,

and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the

________

output from the RTSi pin goes to “L” level, which informs the transmission side that the data

receivable status is ready (output the transfer clock from the IC on the transmission side after

_______

checking that the RTS output has gone to “L” level).

(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi

pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting

right the content of the UARTi reception data in synchronization with the rising edges of the

transfer clock.

(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive

level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes

to “1”.

(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register

is read.

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