H8SX1663 datasheet(640/1158 Pages) RENESAS

640 / 1158 page

Section 11 Programmable Pulse Generator (PPG)

Rev.1.00 Jun. 07, 2006 Page 588 of 1102

REJ09B0294-0100

• PODRL

Bit

Bit Name

Initial

Value

R/W

Description

POD7

POD6

POD5

POD4

POD3

POD2

POD1

POD0

R/W

Output Data Register 7 to 0

For bits which have been set to pulse output by NDERL,

the output trigger transfers NDRL values to this register

during PPG operation. While NDERL is set to 1, the CPU

cannot write to this register. While NDERL is cleared, the

initial output value of the pulse can be set.

11.3.3

Next Data Registers H, L (NDRH, NDRL)

NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on

whether pulse output groups have the same output trigger or different output triggers.

• NDRH

Bit

Bit Name

Initial Value

R/W

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

NDR11

R/W

NDR10

R/W

NDR9

R/W

NDR8

R/W

• NDRL

Bit

Bit Name

Initial Value

R/W

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

NDR3

R/W

NDR2

R/W

NDR1

R/W

NDR0

R/W

H8SX1663 Datasheet(PDF) 640 Page - Renesas Technology Corp

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