HD6432138SW datasheet(298/1061 Pages) RENESAS

298 / 1061 page

Section 9 8-Bit PWM Timers [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 244 of 1004

REJ09B0301-0400

9.2

9.2.1

PWM Register Select (PWSL)

Bit

Initial value

Read/Write

PWCKE

R/W

PWCKS

R/W

—

RS3

R/W

RS0

R/W

RS2

R/W

RS1

R/W

—

PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the

PWM data register.

PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits,

together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the

PWM timer.

PWSL

PCSR

Bit 7

Bit 6

Bit 2

Bit 1

PWCKE

PWCKS

PWCKB

PWCKA

Description

—

Clock input is disabled

(Initial value)

—

φ (system clock) is selected

φ/2 is selected

φ/4 is selected

φ/8 is selected

φ/16 is selected

The PWM resolution, PWM conversion period, and carrier frequency depend on the selected

internal clock, and can be found from the following equations.

Resolution (minimum pulse width) = 1/internal clock frequency

PWM conversion period = resolution

× 256

Carrier frequency = 16/PWM conversion period

Thus, with a 20-MHz system clock (

φ), the resolution, PWM conversion period, and carrier

frequency are as shown below.

HD6432138SW Datasheet(PDF) 298 Page - Renesas Technology Corp

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