HD6432138SW datasheet(118/1061 Pages) RENESAS

118 / 1061 page

Section 2 CPU

Rev. 4.00 Jun 06, 2006 page 64 of 1004

REJ09B0301-0400

2.8.3

Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address

(vector) from the exception vector table and branches to that address.

Types of Exception Handling and Their Priority: Exception handling is performed for resets,

interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their

priority. Trap instruction exception handling is always accepted in the program execution state.

Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.

Table 2.7

Exception Handling Types and Priority

Priority

Type of Exception

Detection Timing

Start of Exception Handling

High

Reset

Synchronized with clock

Exception handling starts

immediately after a low-to-high

transition at the

RES pin, or

when the watchdog timer

overflows.

Interrupt

End of instruction

execution or end of

exception-handling

sequence*

When an interrupt is requested,

exception handling starts at the

end of the current instruction or

current exception-handling

sequence.

Low

Trap instruction

When TRAPA instruction

is executed

Exception handling starts when

a trap (TRAPA) instruction is

executed.*

Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediately after reset exception handling.

2. Trap instruction exception handling is always accepted in the program execution state.

Reset Exception Handling: After the

RES pin has gone low and the reset state has been entered,

when

RES goes high again, reset exception handling starts. When reset exception handling starts

the CPU fetches a start address (vector) from the exception vector table and starts program

execution from that address. All interrupts, including NMI, are disabled during reset exception

handling and after it ends.

Interrupt Exception Handling and Trap Instruction Exception Handling: When interrupt or

trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes

the program counter and other control registers onto the stack. Next, the CPU alters the settings of

the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from

the exception vector table and program execution starts from that start address.

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