HD6432138SW datasheet(117/1061 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Jun 06, 2006 page 63 of 1004

REJ09B0301-0400

End of bus request

Bus request

Program execution

state

Bus-released state

Sleep mode

Exception-handling state

External interrupt

Software standby mode

RES = high

Reset state*1

STBY = high, RES = low

Hardware standby mode*2

Power-down state*3

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs whenever

RES

goes low. A transition can also be made to the reset state when the watchdog timer overflows.

From any state, a transition to hardware standby mode occurs when

STBY goes low.

The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details,

refer to section 24, Power-Down State.

SLEEP

instruction

with

LSON = 0,

SSBY = 0

Interrupt

request

End of bus

request

Bus

request

Request for

exception

handling

End of

exception

handling

SLEEP

instruction

with

LSON = 0,

PSS = 0,

SSBY = 1

Figure 2.15 State Transitions

2.8.2

Reset State

When the

RES input goes low all current processing stops and the CPU enters the reset state. All

interrupts are disabled in the reset state. Reset exception handling starts when the

RES signal

changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14,

Watchdog Timer.

HD6432138SW Datasheet(PDF) 117 Page - Renesas Technology Corp

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