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HD6432138SW Datasheet(PDF) 1013 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 1013 Page - Renesas Technology Corp |
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1013 / 1061 page ![]() Appendix B Internal I/O Registers Rev. 4.00 Jun 06, 2006 page 959 of 1004 REJ09B0301-0400 STR1—Status Register 1 H'FFF6 HIF STR2—Status Register 2 H'FFFE HIF 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R 3 C/ D 0 R R 0 OBF 0 R/(W) R 2 DBU 0 R/W R 1 IBF 0 R R Bit Initial value Slave R/W Host R/W Output data register full 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit 1 [Setting condition] When the slave processor writes to ODR User-defined bits Input data register full 0 [Clearing condition] When the slave processor reads IDR 1 [Setting condition] When the host processor writes to IDR Command/data 0 Contents of input data register (IDR) are data 1 Contents of input data register (IDR) are a command DADR0—D/A Data Register 0 H'FFF8 D/A Converter DADR1—D/A Data Register 1 H'FFF9 D/A Converter 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 0 0 R/W 2 0 R/W 1 0 R/W Bit Initial value Read/Write Stores data for D/A conversion |
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