HD6432138SW datasheet(1012/1061 Pages) RENESAS

Part #	HD6432138SW

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1061 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1012 / 1061 page

Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 958 of 1004

REJ09B0301-0400

IDR1—Input Data Register 1

H'FFF4

HIF

IDR2—Input Data Register 2

H'FFFC

HIF

IDR7

—

IDR6

—

IDR5

—

IDR4

—

IDR3

—

IDR0

—

IDR2

—

IDR1

—

Bit

Initial value

Slave R/W

Host R/W

Stores host data bus contents at rise of

IOW when CS is low

ODR1—Output Data Register 1

H'FFF5

HIF

ODR2—Output Data Register 2

H'FFFD

HIF

ODR7

—

R/W

ODR6

—

R/W

ODR5

—

R/W

ODR4

—

R/W

ODR3

—

R/W

ODR0

—

R/W

ODR2

—

R/W

ODR1

—

R/W

Bit

Initial value

Slave R/W

Host R/W

ODR contents are output to the host data bus

when HA0 is low,

CS is low, and IOR is low

TISR—Timer Input Select Register

H'FFF5

TMRY

—

R/W

—

Bit

Initial value

Read/Write

Input select

IVG signal is selected (H8S/2138 Group)

External clock/reset input is disabled (H8S/2134 Group)

VSYNCI/TMIY (TMCIY/TMRIY) is selected

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