HD6432138SW datasheet(963/1061 Pages) RENESAS

963 / 1061 page

Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 909 of 1004

REJ09B0301-0400

LPWRCR—Low-Power Control Register

H'FF85

System

DTON

R/W

LSON

R/W

NESEL

R/W

EXCLE

R/W

—

Bit

Initial value

Read/Write

Subclock input enable

Subclock input from EXCL pin is disabled

Subclock input from EXCL pin is enabled

Noise elimination sampling frequency select

Sampling at

φ divided by 32

Sampling at

φ divided by 4

Low-speed on flag

• When a SLEEP instruction is executed in high-speed mode or

medium-speed mode, a transition is made to sleep mode, software

standby mode, or watch mode*

• When a SLEEP instruction is executed in subactive mode, a transition

is made to watch mode, or directly to high-speed mode

• After watch mode is cleared, a transition is made to high-speed mode

• When a SLEEP instruction is executed in high-speed mode a

transition is made to watch mode or subactive mode*

• When a SLEEP instruction is executed in subactive mode, a transition

is made to subsleep mode or watch mode

• After watch mode is cleared, a transition is made to subactive mode

Direct-transfer on flag

• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,

a transition is made to sleep mode, software standby mode, or watch mode*

• When a SLEEP instruction is executed in subactive mode, a transition is made to

subsleep mode or watch mode

• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,

a transition is made directly to subactive mode*, or a transition is made to sleep mode

or software standby mode

• When a SLEEP instruction is executed in subactive mode, a transition is made directly

to high-speed mode, or a transition is made to subsleep mode

Note: * When a transition is made to watch mode or subactive mode,

high-speed mode must be set.

Note: * When a transition is made to watch mode or subactive mode, high-speed mode must

be set.

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