HD6432138SW datasheet(954/1061 Pages) RENESAS

954 / 1061 page

Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 900 of 1004

REJ09B0301-0400

DTCER—DTC Enable Register

H'FEEE to H'FEF2

DTC

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

Read/Write

DTC activation enable

DTC activation by interrupt is disabled

[Clearing conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

DTC activation by interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers

have not ended

DTVECR—DTC Vector Register

H'FEF3

DTC

SWDTE

R/(W)*

DTVEC6

R/W

DTVEC5

R/W

DTVEC4

R/W

DTVEC3

R/W

DTVEC0

R/W

DTVEC2

R/W

DTVEC1

R/W

Bit

Initial value

Read/Write

Note: *

Sets vector number for DTC software activation

DTC software activation enable

DTC software activation is disabled

[Clearing condition]

When the DISEL bit is 0 and the specified number of transfers have

not ended

DTC software activation is enabled

[Holding conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

• During software-activated deta transfer

A value of 1 can always be written to the SWDTE bit, but 0 can only be written

after 1 is read.

HD6432138SW Datasheet(PDF) 954 Page - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 954 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL