HD6432138SW datasheet(785/1061 Pages) RENESAS

785 / 1061 page

Section 25 Electrical Characteristics

Rev. 4.00 Jun 06, 2006 page 731 of 1004

REJ09B0301-0400

3. Block erase time (shows the total period for which the E-bit in FLMCR1 is set. It does

not include the erase verification time.)

4. Maximum programming time (tP (max))

tP (max) = wait time after P-bit setting (z)

× maximum programming count (N))

5. Number of times when the wait time after P-bit setting (z) = 200 µs.

The number of writes should be set according to the actual set value of (z) to allow

programming within the maximum programming time (tP (max)).

6. Maximum erase time (tE (max))

tE (max) = Wait time after E-bit setting (z)

× maximum erase count (N))

7. Number of times when the wait time after E-bit setting (z) = 10 ms.

The number of erases should be set according to the actual set value of (z) to allow

erasing within the maximum erase time (tE (max)).

25.2.7

Usage Note

(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference

values for electrical characteristics shown in this manual. However, actual performance

figures, operating margins, noise margins, and other properties may vary due to differences in

the manufacturing process, on-chip ROM, layout patterns, etc.

When system evaluation testing is carried out using the F-ZTAT version, the same evaluation

tests should also be conducted for the mask ROM version when changing over to that version.

(2) On-chip power supply step-down circuit

The H8S/2138 F-ZTAT does not incorporate an internal power supply step-down circuit.

When changing over to F-ZTAT versions or mask ROM versions incorporating an internal

step-down circuit, the V

CC2 pin has the same pin location as the VCL pin in a step-down circuit.

Therefore, note that the circuit patterns differ between these two types of products.

HD6432138SW Datasheet(PDF) 785 Page - Renesas Technology Corp