HD6432138SW datasheet(531/1061 Pages) RENESAS

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Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 477 of 1004

REJ09B0301-0400

Bit 5—I

2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag

(IRTR): Indicates that the I

2C bus interface has issued an interrupt request to the CPU, and the

source is completion of reception/transmission of one frame in continuous transmission/reception

for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1

at the same time.

IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by

reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically

when the IRIC flag is cleared to 0.

Bit 5

IRTR

Description

Waiting for transfer, or transfer in progress

(Initial value)

[Clearing conditions]

1. When 0 is written in IRTR after reading IRTR = 1

2. When the IRIC flag is cleared to 0

Continuous transfer state

[Setting conditions]

• In I2C bus interface slave mode

When the TDRE or RDRF flag is set to 1 when AASX = 1

• In other modes

When the TDRE or RDRF flag is set to 1

Bit 4—Second Slave Address Recognition Flag (AASX): In I

2C bus format slave receive mode,

this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in

SARX.

AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is

also cleared automatically when a start condition is detected.

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