HD6432138SW datasheet(468/1061 Pages) RENESAS

468 / 1061 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 4.00 Jun 06, 2006 page 414 of 1004

REJ09B0301-0400

Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not

affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/

E bit in

SMR.

Bit 2

SINV

Description

TDR contents are transmitted without modification

(Initial value)

Receive data is stored in RDR without modification

TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Bit 1—Reserved: This bit cannot be modified and is always read as 1.

Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be

written in this bit.

Bit 0

SMIF

Description

Normal SCI mode

(Initial value)

Reserved mode

15.2.10

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.

When bit MSTP7, MSTP6, or MSTP5 is set to 1, SCI0, SCI1, or SCI2 operation, respectively,

stops at the end of the bus cycle and a transition is made to module stop mode. For details, see

section 24.5, Module Stop Mode.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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