HD6432138SW datasheet(418/1061 Pages) RENESAS

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Section 13 Timer Connection [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 364 of 1004

REJ09B0301-0400

13.3.6

Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)

By using the timer connection FRT and TMRY, it is possible to automatically generate internal

signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is

synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the

IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in

synchronization with the IHG signal.

The contents of OCRA in the FRT are updated by the automatic addition of the contents of

OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the

0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of

the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR

addition, and reset by a compare-match after an OCRAF addition.

The IHG signal is the TMRY 8-bit timer output. TMRY is set to count internal clock pulses, and

to be cleared on TCORA compare-match, to fix the period and set the timer output. TCORB is set

so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and

the rise of the IVG signal can be treated in the same way as a TCORA compare-match.

The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG

signal, and has a 1 interval of 6 system clock periods.

Examples of settings of TCORA, TCORB, TCR, and TCSR in TMRY, and OCRAR, OCRAF,

and TCR in the FRT, are shown in table 13.8, and the IHG signal/IVG signal timing chart is

shown in figure 13.8.

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