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HD6432138SW Datasheet(PDF) 390 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 390 Page - Renesas Technology Corp |
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390 / 1061 page ![]() Section 12 8-Bit Timers Rev. 4.00 Jun 06, 2006 page 336 of 1004 REJ09B0301-0400 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.14 shows this operation. φ Address TCNT address Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle by CPU Counter write data Figure 12.14 Contention between TCNT Write and Increment |
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