| Electronic Components Datasheet Search |
|
HD6432138SW Datasheet(PDF) 389 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432138SW Datasheet(HTML) 389 Page - Renesas Technology Corp |
|
389 / 1061 page ![]() Section 12 8-Bit Timers Rev. 4.00 Jun 06, 2006 page 335 of 1004 REJ09B0301-0400 12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows this operation. φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 T1 T2 TCNT write cycle by CPU Figure 12.13 Contention between TCNT Write and Clear |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |