HD6432138SW datasheet(368/1061 Pages) RENESAS

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Section 12 8-Bit Timers

Rev. 4.00 Jun 06, 2006 page 314 of 1004

REJ09B0301-0400

TCR

STCR

Bit 2

Bit 1

Bit 0

Bit 1

Bit 0

Channel

CKS2 CKS1 CKS0 ICKS1 ICKS0 Description

—

Clock input disabled

(Initial value)

001

—

φ/8 internal clock source, counted on the falling edge

001

—

φ/2 internal clock source, counted on the falling edge

010

—

φ/64 internal clock source, counted on the falling edge

010

—

φ/32 internal clock source, counted on the falling edge

011

—

φ/1024 internal clock source, counted on the falling edge

011

—

φ/256 internal clock source, counted on the falling edge

—

Counted on TCNT1 overflow signal*

—

Clock input disabled

(Initial value)

001

—

φ/8 internal clock source, counted on the falling edge

001

—

φ/2 internal clock source, counted on the falling edge

010

—

φ/64 internal clock source, counted on the falling edge

010

—

φ/128 internal clock source, counted on the falling edge

011

—

φ/1024 internal clock source, counted on the falling edge

011

—

φ/2048 internal clock source, counted on the falling edge

—

Counted on TCNT0 compare-match A*

—

Clock input disabled

(Initial value)

—

Counted on

φ internal clock source

010

—

φ/2 internal clock source, counted on the falling edge

011

—

φ/4 internal clock source, counted on the falling edge

—

Clock input disabled

—

Clock input disabled

(Initial value)

001

—

φ/4 internal clock source, counted on the falling edge

010

—

φ/256 internal clock source, counted on the falling edge

011

—

φ/2048 internal clock source, counted on the falling edge

—

Clock input disabled

Common 1

—

External clock source, counted at rising edge

—

External clock source, counted at falling edge

—

External clock source, counted at both rising and falling

edges

Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0

compare-match signal, no incrementing clock will be generated. Do not use this setting.

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