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M24C01WDW6TP Datasheet(PDF) 16 Page - STMicroelectronics

Part # M24C01WDW6TP
Description  16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I짼C bus EEPROM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24C01WDW6TP Datasheet(HTML) 16 Page - STMicroelectronics

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Device operation
M24C16, M24C08, M24C04, M24C02, M24C01
16/34
Figure 9.
Read mode sequences
1.
The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must
be identical.
3.7
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
The device has an internal address counter which is incremented each time a byte is read.
3.7.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 9) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
DEV SEL *
BYTE ADDR
DEV SEL
DATA OUT 1
AI01942
DATA OUT N
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
DATA OUT N
DEV SEL *
BYTE ADDR
SEQUENTIAL
RANDOM
READ
DEV SEL *
DATA OUT 1
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK


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