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ST10F280 Datasheet(PDF) 63 Page - STMicroelectronics

Part # ST10F280
Description  16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PDF  186 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 63 Page - STMicroelectronics

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11.2.1.2 - Mode 1: Symmetrical PWM
Generation (Center Aligned PWM)
Mode 1 is selected by setting the respective bit
XPMx in register XPWMCON1 to ‘1’. In this mode
the timer XPTx of the respective XPWM channel
is counting up until it reaches the value in the
associated period shadow register.
Upon the next count pulse the count direction is
reversed and the timer starts counting down now
with subsequent count pulses until it reaches the
value 0000H. Upon the next count pulse the count
direction is reversed again and the count cycle is
repeated with the following count pulses.
The XPWM output signal is switched to a high
level when the timer contents are equal to or
greater than the contents of the pulse width
shadow register while the timer is counting up.
The signal is switched back to a low level when
the respective timer has counted down to a value
below the contents of the pulse width shadow reg-
ister. So in mode 1 this PWM value controls both
edges of the output signal.
Note that in mode 1 the period of the PWM signal
is twice the period of the timer:
PWM_PeriodMode1 = 2 * ([XPPx] + 1)
The figure below illustrates the operation and out-
put waveforms of a XPWM channel in mode 1 for
different values in the pulse width register.
This mode is referred to as Center Aligned PWM,
because the value in the pulse width (shadow)
register effects both edges of the output signal
symmetrically.
Figure 21 : Operation and Output Waveform in Mode 1
1
7
6
5
3
4
2
1
0
1
0
XPPx
Period=7
XPTx Count
Value
XPWx Pulse
Width=0
XPWx=1
XPWx=2
XPWx=4
XPWx=6
XPWx=7
XPWx=8
Latch Shadow Registers
Interrupt Reques
Change Count
LSR
Duty Cycle
100%
87.5%
75%
50%
25%
12.5%
0%
0
2
7
6
5
4
3
2
1
Direction
LSR



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