AM261...ZFG datasheet(160/218 Pages) TI2

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tO16t

O15

OSPI_DQS

OSPI_D[i:0]

Figure 6-54. OSPI Timing Requirements – PHY DDR with External Board Loopback or DQS

6.11.5.13.2.2.2.3 OSPI0 Switching Characteristics - PHY DDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI_CLK

12.5

tw(CLKL)

Pulse duration, OSPI_CLK low

0.475P(1) - 0.3

tw(CLKH)

Pulse duration, OSPI_CLK high

0.475P(1) - 0.3

td(CSn-CLK)

Delay time, OSPI_CSn[1:0] active edge

to OSPI_CLK rising edge

0.475P(1) - (0.975

× M(2) × R(4))

0.525P(1) - (1.025

× M(2) × R(4)) + 7

td(CLK-CSn)

Delay time, OSPI_CLK rising edge to

OSPI_CSn[1:0] inactive edge

0.475P(1) + (0.975

× N(3) × R(4)) - 7

0.525P(1) + (1.025

× N(3) × R(4))

td(CLK-D)

Delay time, OSPI_CLK active edge to

OSPI_D[7:0] transition

1.8V

–1.45

–3.4

3.3V

–1.45

–3.6

(1)

P = OSPI_CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = REFCLK cycle time in ns

tO4t

tO3t

tO5t

tO2t

tO1t

OSPI_CSn

OSPI_CLK

OSPI_D[i:0]

Figure 6-55. OSPI Switching Characteristics – PHY DDR

6.11.5.13.2.3 OSPI1 Without Data Training

Note

Timing parameters defined in this section are only applicable for the OSPI1 interface when data

training is not implemented and DLL delays are configured as described in OSPI1 DLL Delay Mapping

for PHY SDR Timing Modes and OSPI1 DLL Delay Mapping for PHY DDR Timing Modes.

6.11.5.13.2.3.1 OSPI1 PHY SDR Timing

6.11.5.13.2.3.1.1 OSPI1 DLL Delay Mapping for PHY SDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT

FIELD

DELAY VALUE

Transmit

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x20

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

www.ti.com

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