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IS25LP256D-RJLE-TY Datasheet(PDF) 44 Page - Integrated Silicon Solution, Inc |
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IS25LP256D-RJLE-TY Datasheet(HTML) 44 Page - Integrated Silicon Solution, Inc |
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44 / 179 page ![]() IS25LP256D IS25WP256D Integrated Silicon Solution, Inc.- www.issi.com 44 Rev A15 08/05/2024 8.2 COMMAND SET SUMMARY Extended Addressing To accommodate addressing above 128Mb (24-bit), there are three options: 1. New instructions with 4-byte (32-bit) address. See Table 8.2. 2. 4-byte addressing with the 3-byte address instructions: For backward compatibility to the 3-byte address instructions, the standard instructions can be used in conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]) or Enter 4-byte Address Mode to switch from 3 bytes to 4 bytes of address field. When EXTADD bit is set to 1 or Enter 4-byte Address Mode command is issued only in the case that EXTADD bit = 0, the instructions are changed to require 4-byte (32-bit) for the address field. See Table 8.3. 3. 3-byte addressing with the 3-byte address instructions: For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction with the Bank Address Register. See Table 8.3. • The Bank Address Register is used to switch between 128Mbit (16Mbyte) banks of memory, the standard 3- byte address selects an address within the bank selected by the Bank Address Register. o The host system writes the Bank Address Register to access beyond the first 128Mbit of memory. o This applies to read, erase, and program commands. • The Bank Address Register provides the high order (4th) byte of address, which is used to address the available memory at addresses greater than 128Mbit. • Bank Address Register bits are volatile. o On power up, the default is Bank0 (the lowest address 16 Mbytes). • For Read, the device will continuously transfer out data until the end of the array. o There is no bank to bank delay. o The Bank Address Register is not updated. o The Bank Address Register value is used only for the initial address of an access. Table 8.1 Bank Address Map Bank Address Register Bit 0 Bank Memory Array Address Range 0 0 00000000h 00FFFFFFh 1 1 01000000h 01FFFFFFh |
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